1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for assuring consistency of translated instructions being executed by a microprocessor which dynamically translates instructions from a target to a host instruction set.
2. History of the Prior Art
Recently, a new microprocessor was developed which combines a simple but very fast host processor (called a “morph host”) and software (referred to as “code morphing software”) to execute application programs designed for a processor having an instruction set different than the instruction set of the morph host processor. The morph host processor executes the code morphing software which translates the application programs dynamically into host processor instructions which are able to accomplish the purpose of the original software. As the instructions are translated, they are stored in a translation buffer where they may be executed without further translation. Although the initial translation of a program is slow, once translated, many of the steps normally required for hardware to execute a program are eliminated. The new microprocessor has proven able to execute translated “target” programs as fast as the “target” processor for which the programs were designed.
The new microprocessor is described in detail in U.S. Pat. No. 5,832,205, Memory Controller For A Microprocessor For Detecting A Failure Of Speculation On The Physical Nature Of A Component Being Addressed, Kelly et al, Nov. 3, 1998, assigned to the assignee of the present invention.
One reason that the new processor is able to execute programs rapidly is its ability to link together sequences of translations that occur frequently into very long sequences. Linking eliminates many of the steps which would be necessary to retrieve individually the various translations for execution. The process by which this is accomplished is explained in detail in the above-mentioned patent.
One problem that must be resolved for a computer which executes host translations of a target program is that the target program typically defines the sequences of target instructions which are to be executed by presenting a series of addresses at which those instructions are stored to the central processor as those target instructions are to be executed. The central processor reads the address of the instruction next to be executed, fetches that instruction from memory, and executes the instruction. When the target program being executed is defined by such a sequence of addresses yet the instructions being executed are host translations of those instructions which reside at other addresses, it is necessary to determine that each translated host instruction is, in fact, the result of a translation from a target instruction which is at the address (including the effect of address mapping) presented by the target program for execution.
This is an especially difficult problem where sequences of translated instruction have been linked together in the manner described above in order to attain rapid execution.
It is desirable to improve the operation of a computer system which utilizes a microprocessor that translates programs dynamically from target instructions into host instructions able to accomplish the purpose of the original software by rapidly determining that a host instruction is a translation of a target instruction presented for execution.